Apparatus and method for providing a clock signal for testing

ABSTRACT

A clock signal driven device has a clock pin for receiving an externally generated clock signal during normal operation. Internal circuitry coupled to the clock pin is responsive to the externally generated clock signal during normal operation. The device also has a clock source, such as a PLL, that provides an internal clock signal, and an internal clock generator that during a test mode of operation generates from the internal clock signal and asserts on the clock pin a test clock signal. The test clock signal has substantially similar signal characteristics to predefined signal characteristics of the externally generated clock signal. The device&#39;s internal circuitry is responsive to the test clock signal during the test mode of operation.

CROSS-RELATED APPLICATIONS

[0001] This application is a continuation of U.S. application Ser. No.09/507,302, filed Feb. 18, 2000, entitled “Apparatus and Method ForProviding A Clock Signal For Testing,” which is incorporated byreference herein in its entirety.

FIELD OF THE INVENTION

[0002] The present invention relates to an apparatus for and a method ofproviding a clock signal for testing a device.

BACKGROUND OF THE INVENTION

[0003] Semiconductor memories are used to store information in computersystems. As processor speeds continue to increase, the capacity and datarate of memory devices also continues to increase. Typically theprocessor accesses data at a much higher data rate than the data rate ofthe memories. In a memory system, a memory controller provides aninterface between the memories and the processor. The memory controllerand memories are designed to operate in accordance with predefinedspecifications. During the manufacturing process, the memory controllerand memories are tested to ensure that they operate in accordance withthe specifications. For example, the memory controller has inputs orpins that transmit and receive external clock signals, control signalsand data signals. To test the memory controller, the memory controlleris placed in a socket at a test station and the external clock signaland data signals are supplied, varied, and the performance of the memorycontroller is measured. As data rates increase, the frequency of theexternal clock signal increases. Supplying an external high speed clockrequires an expensive high speed tester. Memory controllers are becomingincreasingly sophisticated and may provide an internal high speed clocksignal. Therefore, to reduce cost and simplify testing, an apparatus andmethod that uses the internal high speed clock for testing the memorycontroller is needed.

SUMMARY OF THE INVENTION

[0004] In summary, the present invention provides a clock signal drivendevice that has a clock pin for receiving an externally generated clocksignal during a normal mode of operation. Internal circuitry coupled tothe clock pin is responsive to the externally generated clock signalduring the normal mode of operation. The device also has a clock source,such as a PLL, that provides an internal clock signal, and an internalclock generator that during a test mode of operation generates from theinternal clock signal and asserts on the clock pin a test clock signal.The test clock signal has substantially similar signal characteristicsto predefined signal characteristics of the externally generated clocksignal. The device's internal circuitry is responsive to the test clocksignal during the test mode of operation.

[0005] In a preferred embodiment, the device has two clock pins thatreceive externally generated differential clock signals, and theinternal clock generator generates a pair of differential test clocksignals that are asserted on the two clock pins. A set of clock currentcontrol bits are stored in a register. The internal clock generatorincludes a plurality of clock output drivers for generating each testclock signal, with each of the clock output drivers being selectivelyenabled by a corresponding one of the clock current control bits. Eachclock output driver preferably includes a slew rate controlled predrivecircuit that generates an intermediate clock signal having a slew ratein accordance with a set of slew rate control bits stored in a slew ratecontrol register.

BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Additional objects and features of the invention will be morereadily apparent from the following detailed description and appendedclaims when taken in conjunction with the drawings, in which:

[0007]FIG. 1 is a block diagram a memory system including a memorycontroller and memories during normal operation, the memory controllerand memories having a clock interface circuit that generates an internalclock signal during testing in accordance with an embodiment of thepresent invention.

[0008]FIG. 2 is a block diagram of an alternate embodiment the memorysystem of FIG. 1 that uses differential clock signaling including aclock-to-master (CTM) signal and a complementary clock-to-master (/CTM)signal.

[0009]FIG. 3 is a block diagram of an exemplary device that generates aninternal CTM clock signal in accordance with an embodiment of thepresent invention.

[0010]FIG. 4 is a block diagram of the memory controller in a testenvironment which emulates the memory systems of FIGS. 1 and 2 duringnormal operation.

[0011]FIG. 5 is a circuit diagram of an exemplary data output driver ofFIG. 4.

[0012]FIG. 6 is a circuit diagram of the internal CTM clock generator ofFIG. 4.

[0013]FIG. 7 is a circuit diagram of an exemplary slew rate controlledpredriver of FIGS. 5 and 6.

[0014]FIG. 8 is a flowchart of a method of setting clock current controlbits of a clock current control register of FIG. 3.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] In FIG. 1, the overall architecture of a bus 20 using asingle-ended clock signal is shown. The bus 20 interconnects a memorycontroller 22 and memories 24. In the memory controller 22 and memories24, a bus interface (Bus I/F) 30 provides the connections to andsignaling with the bus 20. The bus 20 is formed of signal lines 20-1,20-2, 20-3 and 20-4 that transmit control, data and clock signals.Physically, on each device 22, 24, the control, data and clock signalsare supplied to and output from external connections, called pins 32,and the signal lines 20 interconnect respective pins 32 on differentdevices. Each device 22, 24 has bus output driver circuits 34 thatconnect to the pins 32 to transmit signals to other devices attached tothe bus 20. In a device, each bus output driver circuit 34 drives asingle signal line of the bus 20. For example, bus output driver 34-1 inthe memory controller 22 drives signal line 20-1. The device may beimplemented using one set of signals, such as CMOS signals, while thebus may be implemented using bus signals different from the CMOSsignals. In one implementation, the CMOS signals use a first set ofvoltage levels to represent information, while the bus uses a second setof voltage levels. The first set of voltage levels is different from thesecond set of voltage levels. The first and second sets of voltagelevels may have different voltage swings. Alternately, the first andsecond sets of voltage levels may also use different numbers ofpredefined voltage levels to encode information. Although multiple busoutput drivers 34 are attached to a single signal line, logic in the businterface 30 synchronizes the transmission of data among the devices onthe bus so that the devices transmit data at times such that thereceivers will properly decode the data. The bus 20 supports signalingwith characteristics that are a function of many factors such as thesystem clock speed, the bus length, the amount of current that theoutput driver circuits can drive, the supply voltages, the spacing andwidth of the wires or traces making up the bus 20, the physical layoutof the bus 20 itself and the resistance of a terminating resistor Z₀ 36that may be attached to some of the signal lines of the bus 20.

[0016] The bus 20 uses current mode signaling. The output drivercircuits 34 are designed to drive the bus 20 with a predetermined amountof current; and the bus receivers 38 are designed to receive the signalssent by the output driver circuits 34 on the bus 20. The amount ofcurrent used to drive the bus is determined, at least in part, by theoutput driver circuits 34 and terminating resistors Z₀ 36.

[0017] A subset of the signal lines 20 connect to terminating resistorsZ₀ 36 which connect to a termination voltage V_(TERM). In oneembodiment, the resistance of the terminating resistors Z₀ 36 is equalto twenty-eight ohms. The termination voltage V_(TERM) can be differentfrom the supply voltage V_(DD). For instance, the supply voltage V_(DD)may be equal to 2.5 volts while the termination voltage V_(TERM) isequal to 1.8 volts. With respect to the bus signals, the terminationvoltage V_(TERM) represents a logical zero. When driving the logicalzero, the output driver circuit 34 does not drive current on itsrespective signal line 20. The bus voltage for a signal at a low levelV_(OL), which represents a logical one, is equal to approximately 1volt. When driving the logical one, the output driver circuit 34 drivesapproximately 36 milliamps on the signal line 20. The voltage swing ofthe signal line is 0.8 volts. In an alternate embodiment, the busvoltage for a signal at the low voltage level represents a logical zero,while the bus termination voltage V_(TERM) represents a logical one.

[0018] In one embodiment, the memories 24 are random access memories(RAMs). In an alternate embodiment, the memories 24 are read-onlymemories (ROMs). Alternately, the bus interface 30 is implemented inother semiconductor devices that use a bus 20 to interconnect varioustypes of integrated circuits such as microprocessors and diskcontrollers.

[0019] In the exemplary memory system of FIG. 1, the memory controller22 supplies an address to the memory 24-1 using the control signal line20-1 to transmit one bit of the address. For simplicity, the othercontrol signal lines are not shown. In the memory 24-1, a bus receiver38-3 receives the address bit and passes the received address to adecoder 42. To receive the entire address, the decoder 42 receivesaddress bits from multiple bus receivers. For simplicity, only one busreceiver 38-3 is shown. The decoder 42 generates the signals to accessthe data stored at a particular row and column of a memory cell array44. To read data from the memory 24, in response to the decoder 42 andother control signals from the bus 20, the memory cell array 44 suppliesdata from the desired address to an input/output (I/O) buffer 46 whichsupplies the data to the bus 20-2 via the output driver 34-4. To writedata to the memory, the memory controller 22 supplies an address asdescribed above. The memory controller 22 also supplies data signals viathe output driver circuits 34 to the bus 20. The memory 24-1 receivesthe address as described above, and also receives the data signals viathe receiver 38-4 and passes the data to the memory cell array 44 forstorage via the I/O buffer 46.

[0020] A single-ended clock signal synchronizes the bidirectionaltransmission of data on the bus 20. When memory devices 24 transmit datatowards the memory controller 22, a clock-to-master (CTM) signalsynchronizes the data transmission. A clock generator 48 supplies theCTM signal on clock signal line 20-3. The master device 22 supplies theclock-from-master signal on clock signal line 20-4 which is terminatedby resistor 36-4. On each device 22, 24, a CTM pin 32-3, 32-7, 32-9receives the CTM signal. In the bus interface 30, a clock interfacecircuit 54 receives the CTM signal from the CTM pin 32-3 at the CTM node50.

[0021] When the memory controller 22 transmits data and/or controlsignals to a memory device 24, the clock-from-master (CFM) signalsynchronizes the transmission on the bus 20. The bus interface 30 of thememory controller 22 provides the CFM signal to clock signal line 20-4via CFM pin 32-4. In the bus interface 30, the CTM node 50 is connectedto the CFM pin 32-4. In this way, the CTM signal becomes the CFM signal.The CFM signal is transmitted via the CFM pin 32-4 on signal line 20-4which is terminated by resistor 36-4. On each device 24, a CFM pin 32-7and 32-10 receives the CFM signal from the memory controller 22.

[0022]FIG. 2 is an alternate embodiment of the bus system of FIG. 1 thatuses differential clock signals. Complementary CTM and CFM signals, /CTMand /CFM, respectively, are used in addition to the CTM and CFM signals.The bus interface 30 of each memory device 24 overlays the bus signallines 20. The clock generator 48 supplies the /CTM signal on signal line20-5 which is received at the /CTM pin 32-15 on each device 24 and atthe /CTM pin 32-13 of the memory controller 22. A /CTM node 52 connectsthe /CTM pin 32-13 to a /CFM pin 32-14 and the /CTM signal becomes the/CFM signal. The /CTM signal is received at a /CFM pin 32-16 on eachdevice 24.

[0023] As shown in FIG. 3, the exemplary memory controller 22 has thebus interface 30 and a core 62. In one implementation, the bus interface30 is a library macrocell that is used in application specificintegrated circuit (ASIC) designs to interface the core of a CMOS ASICdevice to a high-speed bus 20. The CMOS ASIC device may be the memorycontroller 22 (FIG. 1), the memory device 24 (FIG. 1) or otherintegrated circuit.

[0024] The core 62 is the portion of a device that implements aspecified function. In this example, the core 62 includes memorycontroller logic. In another example, referring back to FIG. 1, in amemory 24, the core 62 includes the decoder 42, memory array 44 and I/Obuffer 46.

[0025] In FIG. 3, the bus interface 30 provides the circuitry andsignaling to allow the core 62 to communicate with other devices on thebus 20. One function of the bus interface 30 is to provide an interfacebetween a slow, wide internal CMOS bus to the hi-speed narrow device bus20. The data, control and clock pins, 64, 66, 32-3 and 32-13, connect tothe control, data and clock signal lines, 72, 74, 20-3 and 20-5,respectively, of the bus 20. For simplicity, a single data signal line72, control signal line 74, data pin 64 and control pin 68 are shown. Asdescribed above, each data pin 64 connects to a receiver 38 and to anoutput driver 34. Other output drivers 34 transmit the control signalsonto the control signal lines 74 via control pins 66.

[0026] During normal operation, the external clock signals, the CTM and/CTM signals, are supplied to the CTM and /CTM clock input pins, 32-3and 32-13, by an external clock source via the CTM and /CTM clock signallines, 20-3 and 20-13, respectively.

[0027] During testing, the device 22 internally generates the CTM and/CTM signals, rather than receiving the CTM and /CTM signals from anexternal source. In the core 62, a phase-locked loop (PLL) 80 suppliesan internal PLL clock signal to the clock interface circuit 54. Theinternal PLL clock signal has a frequency approximately equal to 400MHz, and uses CMOS voltage levels rather than the voltage levels of thebus 20. The clock interface circuit 54 generates internal CTM and /CTMsignals from the internal PLL clock signal. The internal CTM and /CTMsignals have substantially the same high voltage level, low voltagelevel, slew rate and frequency as the externally supplied clock signals.In particular, like the external CTM and /CTM clock signals, theinternal CTM and /CTM clock signals have a frequency approximately equalto 400 MHz, a high voltage of about 1.8 volts and a low voltage ofapproximately 1 volt.

[0028] The clock interface circuit 54 receives the CTM and /CTM signalsfrom the CTM and /CTM nodes, respectively, and generates a ˜0° clocksignal and a ˜90° clock signal, and a ˜/0° clock signal and a ˜/90°clock signal from the CTM and /CTM signals, respectively, to synchronizethe transmission of data over the bus 20. The specified number ofdegrees, such as 0° , in the signal name describes the approximate phaseshift of that signal with respect to the CTM and /CTM clock signals atnodes 50 and 52, whether supplied externally or generated internally.The tilde (˜) indicates that the respective clock signal includes anoffset with respect to the actual transmission time of the data over thebus 20 at pins 64.

[0029] A data current control register 82 sets the amount of drivecurrent that the data output drivers 34 use to drive an outgoing datasignal onto a data signal line of the bus. A clock current controlregister 84 connects to the clock interface circuit 54 to set the amountof drive current to drive the internal clock signals during testing. Theclock interface circuit 54 will be further described with reference toFIG. 6.

[0030] A slew rate control (SRC) register 86 supplies slew rate controlbits to the output drivers 34 to set the slew rate of the data andcontrol signals. The SRC register 86 also supplies the slew rate controlbits to the clock interface circuit 54 to set the slew rate of theinternal CTM and /CTM clock signals.

[0031] A logic circuit 88 connects to the data current control register82, clock current control register 84 and slew rate control register 86.The logic circuit 88 determines operational values for the data currentcontrol bits, the clock current control bits and slew rate control bitsin the data current control register 82, the clock current controlregister 84 and the slew rate control register 86, respectively.

[0032] In FIG. 4, the overall architecture of the clock interfacecircuit 54 of the bus interface in the memory controller 22 inaccordance with an embodiment of the present invention is shown. Thedata receiver 38-2 receives the data signal from the data pin 32-2 andthe ˜0° clock signal, and outputs a received data signal. The datasignal at pin 32-2 is received in accordance with an ideal 0° clocksignal, the CTM signal. The ˜0° clock signal is offset with respect tothe actual appearance of the data signal at data pin 32-2 by the set-uptime of the receiver. Similarly, other data receivers receive data inaccordance with the ˜/0° clock signal which is offset with respect tothe actual appearance of the data signal at the data pins by the set-uptime of the receivers. In other words, the ˜/0° clock signal is offsetwith respect to the /CTM signal.

[0033] The data output drive circuit 34-2 drives data to be output ontothe data signal line 20-2 in accordance with the ˜90° clock signal, datacurrent control register and slew rate control register of FIG. 3. The˜90° clock signal includes an offset with respect to the ideal datatransmission time at data pin 32-2. The offset is substantially equal toa delay of a predriver circuit in the output drive circuit 34-2. Becauseof the offset, the output driver circuit 34-2 transmits data at pin 32-2at the ideal data transmission time, that is, synchronized to the CFMclock. Similarly, other data output drive circuits drive data onto thedata signal line in accordance with the complementary ˜/90° clocksignal. The ˜/90° clock signal also includes the offset of thepredriver, and transmits data at pin 32-2 at the ideal complementarydata transmission time, that is, synchronized to the /CFM clock.

[0034] During testing, termination resistor 36-2 connects the data pin32-2 to the termination voltage V_(TERM). The resistor 36-2 has animpedance Z₀ substantially equal to 28 ohms. The cylinder 92 on the datasignal line 20-2 represents the impedance of the data signal line 20-2which is substantially equal to the impedance of the terminationresistor 36-2, that is, 28 ohms.

[0035] The clock interface circuit 54 includes a delay-locked loop (DLL)94 that receives the CTM and /CTM signals from the CTM and /CTM nodes,50 and 52, respectively. The DLL 94 generates the ˜0° clock signal andthe ˜/90° clock signal from the incoming CTM signal at the CTM node 50.The DLL 94 generates the ˜90° clock signal by delaying the incoming CTMsignal from the CTM node 50. The ˜0° clock signal and the ˜90° clocksignal are supplied to at least a subset of the output drivers 34 andreceivers 38 to synchronize the timing of data transmission between thedevice 22 and the bus 20. Similar to the ˜0° and ˜90° clock signals, theDLL 94 also generates the complementary ˜/0° and ˜/90° clock signalsfrom the /CTM signal at the /CTM node 52. The DLL 94 supplies the ˜/0°and ˜/90° clock signals to at least a subset of the data output drivers34 and receivers to synchronize the timing of data transmission betweenthe device 22 and the bus 20.

[0036] When the device 22 is tested, a test clock generator 100 in theclock interface circuit 54 generates and provides the internal CTM and/CTM clock signals at the CTM and /CTM nodes, 50 and 52, rather thanreceiving the external CTM and /CTM clock signals, respectively.

[0037] The PLL 80 supplies the internal PLL clock signal to tri-stateinverter 104. During testing, a PLL clock enable signal from a controlregister in the bus interface activates the tri-state inverter 104. Whenactive, the tri-state inverter 104 supplies the internal PLL clocksignal to a test circuit 106 and a complementary test circuit 108 in thetest-clock generator 100. The test circuit 106 provides the internal CTMclock signal to the CTM node 50. The complementary test circuit 108provides the complementary internal /CTM clock signal to the /CTM node52.

[0038] For testing, the device 22 is placed in a test socket at atesting station. Unlike in normal operation, in test operation, toprevent undesirable reflections while using the internal clock signals,the CTM, CFM, /CTM and /CFM pins, 32-3, 32-4, 32-13 and 32-14, arepulled up to the termination voltage V_(TERM) via 28 ohm terminationresistors, 112, 114, 116 and 118, respectively.

[0039]FIG. 5 is a circuit diagram of an exemplary data output driver34-2 of FIG. 4 that alternately outputs even and odd data on oppositephases of the ˜90° clock signal. Because the data and control outputdrivers are the same, the description of data output driver 34-2 alsoapplies to the control output drivers 34-1. The data output driver 34-2connects to data pin 32-2 which is pulled-up to the termination voltageby the termination resistor 36-2 which has an impedance of 28 ohms. Thedata output driver 34-2 has one or more current-control-data-outputcircuits 132 that are connected together at data node 134. Eachcurrent-control-data-output circuit 132 drives the data node 134 with apredetermined amount of drive current in response to a distinct currentcontrol bit. Current control data output circuit 132-1 is responsive tocurrent control bit 0, and current control data output circuit 132-2 isresponsive to current control bit N.

[0040] Each current-control-data-output circuit 132 has a data inputcircuit 136, a even-odd multiplexing circuit 138, a slew-rate-controlled(SRC) predriver 140, and an output-data-drive block 142. Theoutput-data-drive block 142 has an NMOS drive transistor 144 that sinksa predetermined amount of current from the data node 134 to ground inresponse to an intermediate data signal provided by the SRC predriver140 to its gate. The amount of current that the NMOS drive transistor144 sinks is determined by its width and length. The NMOS drivetransistors 144 of the current-control-data-output circuits 132 arebinary weighted with respect to each other. For example, the NMOS drivetransistor 144-1 of the current-control-data-output circuit 132-1associated with current control bit 0 (CC<0>) is sized to sink an amountof drive current equal to I₀, while the NMOS drive transistor 144-2 ofthe current-control-data-output circuit associated with current controlbit 1 (CC<1>) is sized to sink an amount of drive current equal toone-half of I₀. More generally, where i represents the particularcurrent control bit associated with a current-control-data-outputcircuit 132, the corresponding NMOS drive transistor 144 of thecurrent-control-data-output circuit 132 associated with current controlbit i (CC<i>) is sized to sink an amount of drive current Ii inaccordance with relationship (1) as follows: $\begin{matrix}{I_{i} = {\frac{1}{2^{i}}I_{o}}} & (1)\end{matrix}$

[0041] In sum, all of the current-control-data-output circuits 132 arethe same, except for receiving a distinct current control bit and havingan NMOS drive transistor 144 with a distinct binary weighting.

[0042] The data input circuit 136 receives data bits to be output aseven and odd data. The even data bit is output on the rising edge of the˜90° clock signal, and the odd data bit is output on the falling edge ofthe ˜90° clock signal. The data input circuit 136 also receives one ofthe current control bits that determines whether a respectivecurrent-control-data output circuit 132 will drive the data node 134. Inthe data input circuit 136, a first AND gate 146 receives the even-dataand a second AND gate 148 receives the odd data. Both the first andsecond AND gates, 146 and 148, respectively, receive the current controlbit. When the current control bit is a digital one, the first and secondAND gates, 146 and 148, allow the even-data and the odd-data to beoutput, respectively. For example, when current control bit 0 (cc<0>) isa digital one and the even-data is a digital one, the first AND gate 146outputs a digital one. When current control bit 0 (cc<0>) is a digitalzero, the first and second AND gates, 146 and 148, respectively, outputa digital zero, regardless of the state of the even and odd data, andthat current-control-data-output circuit 132-1 does not drive currentfrom the data node 134.

[0043] In the even-odd-multiplexing circuit 138, first and secondtri-state inverters, 152 and 154, receive the even and odd data signalsfrom the first and second AND gates, 146 and 148, respectively. Theoutputs of the first and second tri-state inverters, 152 and 154,respectively, are connected together. The ˜90° clock signal is suppliedto complementary enable inputs on the first and second tri-stateinverters, 152 and 154, to alternately output the even and odd datasignals, respectively, during alternate phases of the ˜90° clock signalas a multiplexed-data signal. The multiplexed-data signal is supplied tothe slew-rate-controlled predriver 140, and subsequently to theoutput-data-drive block 142. The slew-rate-controlled predriver 140 willbe further described with respect to FIG. 7.

[0044]FIG. 6 includes a more detailed circuit diagram of the test clockgenerator 100 of FIG. 4. The test clock generator 100 provides internalCTM and /CTM clock signals with substantially the same characteristicsas the external CTM and /CTM clock signals that are provided duringnormal operation, thereby eliminating the need for an external clockgenerator. The internal CTM and /CTM clock signals have substantiallythe same frequency, duty cycle, slew rate, low output voltage, highoutput voltage, and voltage range as the external clock signals. Becausethe present invention supplies the internal CTM and /CTM clock signalsto the CTM and /CTM nodes, 50 and 52, respectively, probes can beattached to the CTM, CFM, /CTM and /CFM output pins, 32-3, 32-4, 32-13,and 32-14, respectively, to monitor the respective signals whichprovides additional testing capability.

[0045] For example, the DLL 94 supplies the ˜90° clock signal to theoutput driver circuit 34-1 (FIG. 4). During testing, the ˜90° clocksignal is derived from the internal CTM clock signal at node 50, and hasa ˜90° phase shift with respect to the internal CTM clock signal. Inother words, the ˜90° clock signal includes the offset for the predriverwith respect to the internal CTM clock signal. Therefore, the outputdata will be shifted 90° with respect to the internal CTM clock signal.If the device 22 fails a test, to further identify the cause of thefailure, probes can be attached to the data pin 32-1, the CTM pin 32-3and /CTM pin 32-13 to display the signals on a display and examine therelationship between their timing.

[0046] Because the CTM, CFM, /CTM and /CFM pins, 32-3, 32-4, 32-5 and32-6, respectively, are connected during testing to terminatingresistors 112, 114, 116 and 118 having the same resistance as theterminating resistors in normal operation, twice as much drive currentis needed to drive the CTM and /CTM nodes, 50 and 52, respectively,during testing as compared to normal operation. The amount of drivecurrent to drive the data and clock signals to the same low outputvoltage also depends on process, temperature and internal devicecharacteristics. To more precisely adjust the drive current to providean internal clock signal with substantially the same characteristics asthe external clock signal, the test circuit uses one or morecurrent-controlled-clock output circuits 170 that are similar to thecurrent-controlled-data output circuits 132 of FIG. 5.

[0047] The current-controlled-clock output circuits 170 are connected tothe CTM node 50. Each current-controlled-clock output circuit 170 drivesa predetermined amount of current from the CTM node 50 in response to arespective a distinct clock current control bit from the clock currentcontrol register 84 (FIG. 3). In the test circuit 106, the number ofclock current control bits and the number of current-controlled-clockoutput circuits 170 is preferably the same as the number of data currentcontrol bits and current-control-data-output circuits 132, respectively,of the data output driver 32-1 (FIG. 5).

[0048] In the data input block 172 of the current-controlled-clockoutput circuit 170, the data input is fixed. The input of the AND gate174 is connected to the supply voltage to fix the even data signal to adigital one rather than receiving an even data signal. The input to theAND gate 176 is connected to ground to fix the odd data signal to adigital zero, rather than receiving an odd data signal. Because the datainput to the second AND gate 174 is a digital zero, that is, one inputto the second AND gate 174 is connected to ground, the second AND gate174 always outputs a digital zero, regardless of the state of thecurrent control bit for that AND gate 174. When the current control bitassociated with the data input block becomes active, the first AND gate172 outputs a digital one.

[0049] The even-odd-multiplexing circuit 138 and theslew-rate-controlled predriver 140 are the same as theeven-odd-multiplexing circuit 138 of the data output driver 34-1. Whenthe internal PLL clock enable signal is active and the PLL clock buffer104 is enabled, the internal PLL clock signal alternately enables anddisables the respective tri-state inverters of the even-odd-multiplexingcircuit to alternately output a “1” and a “0”.

[0050] The slew-rate-controlled predriver 140 is the same as theslew-rate-controlled predriver 140 of the data output driver. Theslew-rate-controlled predriver 140 receives the output of the inverters152, 154, and the same slew rate control bits as theslew-rate-controlled predriver 140 of the data output driver. The slewrate control register 86 (FIG. 3) sets the slew rate of the transitionsof the internal CTM clock signal. The slew-rate-controlled predriver 140outputs an adjusted clock signal.

[0051] In the output drive block 180, the adjusted clock signalalternately activates and deactivates the NMOS drive transistors 182,184 to generate the internal CTM clock signal at node 50. Since theinternal PLL clock signal has a fifty percent duty cycle and the eveninput data is fixed to a digital one and the odd input data is fixed toa digital zero, the internal clock signal has a fifty percent dutycycle.

[0052] Because the CTM and CFM pins are both pulled up to 28 ohms, thecombined impedance at the CTM node 50 is 14 ohms rather than 28 ohms andtwice as much drive current is needed to drive the CTM node 50.Similarly, twice as much drive current is needed to drive the /CTM node52. Because twice as much drive current is needed to drive the CTM and/CTM nodes, each current-controlled-clock output circuits 170 sinkstwice as much current as its respective current-controlled-data outputcircuits 132 counterpart. In addition, because the CTM and CFM pins,32-3 and 32-4, are both connected to the termination voltage V_(TERM)via terminating resistors 112 and 114, respectively, during testing, forthe internal CTM clock signal to have the same low output voltage, highoutput voltage, voltage swing, and slew rate as the external clocksignal, the output-clock-drive blocks 180 of the test circuit 106 havetwo output drive transistors 182, 184, rather than the one output drivetransistor 144 of the data output driver 34-1 (FIG. 5). Each drivetransistor 182, 184 has the same geometry (and thus the same operatingcharacteristics) as its respective drive transistor 144 of itscounterpart current-controlled-data output circuit 132.

[0053] Similar to the output-data-drive blocks 132 (FIG. 5), theoutput-clock-drive blocks 170 of the test circuit 106 havebinary-weighted NMOS transistors 182 and 184. In particular, each NMOStransistor 182, 184 of an output-clock-drive block circuit 170 has thesame geometry as the NMOS transistor output-data drive block 132 thatreceives the corresponding data current control bit. Therefore, thedrive transistors of the output-clock-drive blocks 170 closely match andhave the same process variation as the drive transistors of theoutput-data-drive blocks.

[0054] In an alternate embodiment, a single NMOS drive transistor isprovided in the output drive block of the adjustment circuit rather thantwo NMOS drive transistors. The single NMOS drive transistor is sized tosink the same amount of current as the two NMOS drive transistors.Because the single NMOS drive transistor does not have the same geometryas the drive transistors of the data output drivers, the single NMOSdrive transistor has different operating characteristics with respect toprocess variation and the internal clock signal may not provide the samelow output voltage, voltage range and slew rate as the dual NMOS drivertransistor embodiment.

[0055] The complementary internal clock signals, /CTM and /CFM, areprovided via the /CTM and /CFM pins, which are connected together at the/CTM node 52. The /CTM node 52 is connected to a complementary-testcircuit 108. The complementary-test circuit is the same as the testcircuit 106 that was described above, except that in the data inputblock the “1” and “0” are supplied to opposite AND gates.

[0056]FIG. 7 is a circuit diagram of an exemplary slew rate controlledpre-driver 140 used with the present invention. The SRC predriver 140has a plurality of predriver sub-blocks 202, 204, 206. The number ofpredriver sub-blocks may be more or less than the three shown in FIG. 7,depending on the amount of slew rate control required. Generally, therewill be one more predriver sub-block than there are Slew Rate Controlbits.

[0057] Each predriver sub-block 202, 204, 206 has an inverter 208, 210,212 and a passgate pair 214, 216, 218 respectively. One predriversub-block 202 is always enabled with the gate of each transistor of thepassgate pair 214 connected to the supply voltage Vcc and to ground,respectively. The other passgate pairs 216, 218 of the predriversub-blocks 204, 206 connect to the slew rate control bits, Slew RateControl <0> and Slew Rate Control <1>. The slew rate of the predriver140 is adjusted by enabling and disabling the passgates 216, 218 withslew rate control signals on the slew rate control bits.

[0058] In particular, when the slew rate control signal on Slew RateControl bit <1> is high, the passgate pair 216 of the predriversub-block 204 is enabled. The passgate pair 216 increases the rate oftransition between a high voltage level and a low voltage level of anintermediate signal on node 220. When the slew rate control bit <1> islow, the corresponding passgate pair 216 of the predriver sub-block 204is effectively disabled and the slew rate is unaffected. Enabling theadditional passgate pairs of additional predriver sub-blocks 206 furtherincreases the slew rate of the q-node signal.

[0059]FIG. 8 is a flowchart of a method of setting clock current controlbits of a clock current control register of FIG. 5. In step 240, thelogic circuit 88 (FIG. 3) sets the clock current control bits of theclock current control register 84 (FIG. 3) to a predetermined initialvalue that guarantees the generation of a clock signal. In step 242, thelogic circuit 88 (FIG. 3) sets the data current control bits of the datacurrent control register 82 (FIG. 3) to another predetermined initialvalue. In step 244, the logic circuit 88 (FIG. 3) adjusts the setting ofthe data current control bits to provide adjusted data current controlbits so that a specified rail-to-rail voltage swing on the bus ismaintained. In step 246, the logic circuit 88 (FIG. 3) updates the clockcurrent control bits of the clock current control register 84 (FIG. 3)to the same value as the adjusted data current control bits. In step248, after setting the clock current control bits, device testingcontinues.

[0060] U.S. Pat. No. 5,254,883, to Horowitz et al. is herebyincorporated by reference in its entirety as background information on amethod of setting the data current control bits. U.S. patent applicationSer. No. 09/222,590 to Stark et al. is hereby incorporated by referencein its entirety as background information of an alternate embodiment ofan output driver and a method of setting the data current control bits.

[0061] During testing, the slew rate control bits are simultaneouslyadjusted for both the output drivers and the test clock generator 100.While calibrating the current control bits, the voltage level of theoutput data signal changes. To set data current control bits to adesired operating value, a stable internal clock is supplied to the DLL94 (FIG. 3) so that the 9020 clock signal is guaranteed to be suppliedto the output drivers. If the clock current control bits were to bechanged while calibrating the data current control bits, the internalclock signal and therefore the 90° clock signal may disappear andtesting would fail. Therefore, the current control bits for the internalclock generator 100 are stored in a separate register, the clock currentcontrol register 84 (FIG. 3), from the data current control register 82(FIG. 2) that stores the data current control bits.

[0062] The predetermined initial value of the clock and data currentcontrol bits depends on the process used to manufacture the device andthe specification of the bus. Although the predetermined initial valueof the clock current control bits may not be the final value, thepredetermined initial value is sufficient to ensure that the 90° clocksignal will be generated.

[0063] Although the invention was described with respect to a memorycontroller, in another embodiment, the bus interface of the presentinvention provides a high-speed device-to-device interface. In analternate embodiment, the bus interface is used in the memory devices 24(FIG. 1). When using the test-clock generator 100 (FIG. 4) in a memorydevice 24, the CTM and CFM pins, and the /CTM and /CFM pins, are notshorted together. Rather, the memory device uses two pairs ofdifferential clock signals to control their operation. The test-clockgenerator 100 for memory devices 24 therefore generates two pairs ofdifferential clock signals, instead of just one pair of differentialclock signals as described above for the test-clock generator for thememory controller device 22. All four external clock pins for the deviceare connected to termination resistors 112-118 during the test mode ofoperation.

[0064] While the present invention has been described with reference toa few specific embodiments, the description is illustrative of theinvention and is not to be construed as limiting the invention. Variousmodifications may occur to those skilled in the art without departingfrom the true spirit and scope of the invention as defined by theappended claims.

What is claimed is:
 1. A memory controller, comprising: a phasecompensation circuit adapted for receiving a first clock signal, thephase compensation circuit configured to use the first clock signal tosynchronize data communications between the memory controller and amemory device during a first mode of operation; and a clock generatorcircuit coupled to the phase compensation circuit and configured toprovide a second clock signal to the phase compensation circuit during asecond mode of operation, wherein the first and second clock signalshave at least one substantially similar signal characteristic.
 2. Thememory controller of claim 1, wherein the clock generator circuitprovides differential clock signals.
 3. The memory controller of claim1, wherein the first and second clock signals have substantially thesame voltage levels.
 4. The memory controller of claim 1, wherein thefirst and second clock signals have substantially the same frequency. 5.The memory controller of claim 4, wherein the frequency is about 400MHz.
 6. The memory controller of claim 1, further comprising: an outputdriver circuit coupled to the phase compensation circuit and to at leastone data output node, the output driver circuit configured to driveoutgoing data signals on the data output node.
 7. The memory controllerof claim 6, further comprising: a drive current control register coupledto the output driver circuit and configured to set an amount of drivecurrent that the output driver circuit uses to drive the outgoing datasignal on the data output node.
 8. The memory controller of claim 6,further comprising: a slew rate control register coupled to the outputdriver circuit and storing slew rate control data for configuring theoutput driver circuit to control slew rates of data signals applied tothe data output node.
 9. The memory controller of claim 1, furthercomprising: a clock current register coupled to the clock generatorcircuit and configured to set an amount of drive current that the clockgenerator circuit uses to drive the second clock signal on a clockoutput node.
 10. A memory device, comprising: a phase compensationcircuit adapted for receiving a first clock signal, the phasecompensation circuit configured to use the first clock signal tosynchronize data communications between the memory device and a memorycontroller during a first mode of operation; and a clock generatorcircuit coupled to the phase compensation circuit during a second modeof operation, and configured to provide a second clock signal to thephase compensation circuit, wherein the first and second clock signalshave at least one substantially similar signal characteristic.
 11. Thememory device of claim 10, wherein the clock generator circuit providesdifferential clock signals.
 12. The memory device of claim 11, whereinthe clock generator circuit generates two pairs of differential clocksignals.
 13. The memory device of claim 10, wherein the first and secondclock signals have substantially the same voltage levels.
 14. The memorydevice of claim 10, wherein the first and second clock signals havesubstantially the same frequency.
 15. The memory device of claim 14,wherein the frequency is about 400 MHz.
 16. The memory device of claim10, further comprising: an output driver circuit coupled to the phasecompensation circuit and to at least one data output node, the outputdriver circuit configured to drive outgoing data signals on the dataoutput node.
 17. The memory device of claim 16, further comprising: adrive current control register coupled to the output driver circuit andconfigured to set an amount of drive current that the output drivercircuit use to drive the outgoing data signal on the data output node.18. The memory device of claim 16, further comprising: a slew ratecontrol register coupled to the output driver circuit and storing slewrate control data for configuring the output driver circuit to controlslew rates of data signals applied to the data output node.
 19. Thememory device of claim 16, further comprising: a clock current registercoupled to the clock generator circuit and configured to set an amountof drive current that the clock generator circuit uses to drive thesecond clock signal on a clock output node.
 20. A method of providingclock signals for testing a memory controller, comprising: in the memorycontroller: generating a test clock signal during a first mode ofoperation, wherein the test clock signal has substantially similarsignal characteristics to a clock signal received by the memorycontroller during a second mode of operation.
 21. The method of claim20, wherein the clock signal and the test clock signal are differentialclock signals.
 22. The method of claim 20, wherein the clock signal andthe test clock signal have substantially the same voltage levels. 23.The method of claim 20, wherein the clock signal and the test clocksignal have substantially the same frequency.
 24. The method of claim23, wherein the frequency is about 400 MHz.
 25. The method of claim 20,further comprising: setting an amount of drive current that a clockgenerator circuit uses to drive the test clock signal on a clock outputnode.
 26. A method of providing clock signals for testing a memorydevice, comprising: in the memory device: generating a test clock signalduring a first mode of operation, wherein the test clock signal hassubstantially similar signal characteristics to a clock signal receivedby the memory device during a second mode of operation.
 27. The methodof claim 26, wherein the clock signal and the test clock signal havesubstantially the same voltage levels.
 28. The method of claim 26,wherein the clock signal and the test clock signal have substantiallythe same frequency.
 29. The method of claim 28, wherein the frequency isabout 400 MHz.
 30. The method of claim 26, further comprising: settingan amount of drive current that a clock generator circuit uses to drivethe test clock signal on a clock output node.
 31. A memory controller,comprising: means for receiving a clock signal for synchronizing datacommunications between the memory controller and a memory device duringa first mode of operation; and means for providing a test clock signalduring a second mode of operation for testing the memory controller,wherein the clock signal and the test clock signal have at least onesubstantially similar signal characteristic.
 32. A memory device,comprising: means for receiving a clock signal for synchronizing datacommunications between the memory device and a memory controller duringa first mode of operation; and means for providing a test clock signalduring a second mode of operation for testing the memory device, whereinthe clock signal and the test clock signal have at least onesubstantially similar signal characteristic.